rev.2.00 jan 31, 2006 page 1 of 7 HD74HC195 4-bit parallel-access shift register rej03d0590?0200 (previous ade-205-467) rev.2.00 jan 31, 2006 description this shift register features parallel inputs, parallel outputs, j- k serial inputs, shift/load control input, and a direct overriding clear. this shift register can opera te in two modes: parallel load; shift from q a towards q d . parallel loading is accomplished by applying the four bits of data, and taking the shift/load control input low. the data is loaded into the associated flip-flops and appears at the ou tputs after the positive transition of the clock input. during parallel loading, serial data flow is inhibited. serial sh ifting occurs synchronously when the shift/load control input is high. serial data for this mode is entered at the j- k inputs. these inputs allow the first stage to perform as a j- k or toggle flip-flop as shown in the function table. features ? high speed operation: t pd (clock to q) = 13 ns typ (c l = 50 pf) ? high output current: fa nout of 10 lsttl loads ? wide operating voltage: v cc = 2 to 6 v ? low input current: 1 a max ? low quiescent supply current: i cc (static) = 4 a max (ta = 25c) ? ordering information part name package type package code (previous code) package abbreviation taping abbreviation (quantity) HD74HC195p dilp-16 pin prdp0016ae-b (dp-16fv) p ? function table inputs serial parallel outputs clear shift/ load clock j k a b c d q a q b q c q d q d l x x x x x x x x l l l l h h l x x a b c d a b c d d h h l x x x x x x q a0 q b0 q c0 q d0 q d0 h h l h x x x x q a0 q a0 q bn q cn q cn h h l l x x x x l q an q bn q cn q cn h h h h x x x x h q an q bn q cn q cn h h h l x x x x q an q an q bn q cn q cn h : high level (steady state) l : low level (steady state) x : don?t care : transition from low to high level. a, b, c, d : the level of steady-state input at inputs a, b, c or d respectively. q a0 , q b0 , q c0 , q d0 : the level of q a , q b , q c or q d respectively, before the indicated steady-state input conditions were established. q an , q bn , q cn , q dn : the level of q a , q b , q c or q d respectively before the most recent transition of the clock.
HD74HC195 rev.2.00 jan 31, 2006 page 2 of 7 pin arrangement 1 2 3 4 5 6 7 8 clear j k a b c d gnd v cc q a q b q c q d q d clock shift/load 16 15 14 13 12 11 10 9 (top view) d k clear j b c a ck q b q a q d q d q c serial inputs parallel inputs outputs shift/load timing diagram clock clear serial inputs shift/load parallel data inputs outputs clear load h l h l j k a b c d q a q b q c q d serial shift serial shift
HD74HC195 rev.2.00 jan 31, 2006 page 3 of 7 logic diagram d shift/ load clock clear q d q d q c q b q a cb a k j v cc v cc d c cq c l c l d c cq c l c l d c cq c l c l d c cq c l c l absolute maximum ratings item symbol ratings unit supply voltage range v cc ?0.5 to 7.0 v input / output voltage v in , v out ?0.5 to v cc +0.5 v input / output diode current i ik , i ok 20 ma output current i o 25 ma v cc , gnd current i cc or i gnd 50 ma power dissipation p t 500 mw storage temperature tstg ?65 to +150 c note: the absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. recommended operating conditions item symbol ratings unit conditions supply voltage v cc 2 to 6 v input / output voltage v in , v out 0 to v cc v operating temperature ta ?40 to 85 c 0 to 1000 v cc = 2.0 v 0 to 500 v cc = 4.5 v input rise / fall time *1 t r , t f 0 to 400 ns v cc = 6.0 v notes: 1. this item guarantees maxi mum limit when one input switches. waveform: refer to test circuit of switching characteristics.
HD74HC195 rev.2.00 jan 31, 2006 page 4 of 7 electrical characteristics ta = 25c ta = ?40 to+85c item symbol v cc (v) min typ max min max unit test conditions 2.0 1.5 ? ? 1.5 ? 4.5 3.15 ? ? 3.15 ? v ih 6.0 4.2 ? ? 4.2 ? v 2.0 ? ? 0.5 ? 0.5 4.5 ? ? 1.35 ? 1.35 input voltage v il 6.0 ? ? 1.8 ? 1.8 v 2.0 1.9 2.0 ? 1.9 ? 4.5 4.4 4.5 ? 4.4 ? 6.0 5.9 6.0 ? 5.9 ? i oh = ?20 a 4.5 4.18 ? ? 4.13 ? i oh = ?4 ma v oh 6.0 5.68 ? ? 5.63 ? v vin = v ih or v il i oh = ?5.2 ma 2.0 ? 0.0 0.1 ? 0.1 4.5 ? 0.0 0.1 ? 0.1 6.0 ? 0.0 0.1 ? 0.1 i ol = 20 a 4.5 ? ? 0.26 ? 0.33 i ol = 4 ma output voltage v ol 6.0 ? ? 0.26 ? 0.33 v vin = v ih or v il i ol = 5.2 ma input current iin 6.0 ? ? 0.1 ? 1.0 a vin = v cc or gnd quiescent supply current i cc 6.0 ? ? 4.0 ? 40 a vin = v cc or gnd, iout = 0 a
HD74HC195 rev.2.00 jan 31, 2006 page 5 of 7 switching characteristics (c l = 50 pf, input t r = t f = 6 ns) ta = 25c ta = ?40 to +85c item symbol v cc (v) min typ max min max unit test conditions 2.0 ? ? 6 ? 5 4.5 ? ? 30 ? 24 maximum clock frequency f max 6.0 ? ? 35 ? 28 mh z 2.0 ? ? 140 ? 175 4.5 ? 13 28 ? 35 t phl 6.0 ? ? 24 ? 30 ns 2.0 ? ? 140 ? 175 4.5 ? 13 28 ? 35 t plh 6.0 ? ? 24 ? 30 ns clock to q 2.0 ? ? 150 ? 190 4.5 ? 15 30 ? 38 propagation delay time t phl 6.0 ? ? 26 ? 33 ns clear to q 2.0 80 ? ? 100 ? 4.5 16 7 ? 20 ? pulse width t w 6.0 14 ? ? 17 ? ns clock to clear 2.0 100 ? ? 125 ? 4.5 20 6 ? 25 ? 6.0 17 ? ? 21 ? ns a, b, c, d, j, k to clock 2.0 100 ? ? 125 ? 4.5 20 13 ? 25 ? setup time t su 6.0 17 ? ? 21 ? ns shift/load to clock 2.0 0 ? ? 0 ? 4.5 0 ?3 ? 0 ? hold time t h 6.0 0 ? ? 0 ? ns any input except shift/load 2.0 75 ? ? 95 ? 4.5 15 8 ? 19 ? 6.0 13 ? ? 16 ? ns shift/load to clock 2.0 25 ? ? 31 ? 4.5 5 0 ? 6 ? removal time t rem 6.0 4 ? ? 5 ? ns clear inactive to clock 2.0 ? ? 75 ? 95 4.5 ? 5 15 ? 19 output rise/fall time t tlh t thl 6.0 ? ? 13 ? 16 ns input capacitance cin ? ? 5 10 ? 10 pf
HD74HC195 rev.2.00 jan 31, 2006 page 6 of 7 test circuit v cc clear z out = 50 ? input v cc q a to q d a to d l r clock s 1 s 0 c l = 50 pf output c l = 50 pf output q d pulse generator note : 1. c l includes probe and jig capacitance. see function table waveforms clear clock v cc 0 v 1. input pulse : prr 1 mhz, zo = 50 ?, t r 6 ns, t f 6 ns 2. a clear pulse is applied prior to each test. 3. propagation delay times (tplh and tphl ) are measured at tn+1. proper shifting of data is verified at tn+4 with a functional test. 4. j and k inputs are tested the same as data a, b, c and d inputs except that shift / load input remains high. 5. tn : bit time before clocking transition. 6. tn+1 : bit time after one clocking transition. 7. tn+4 : bit time after four clocking transition. notes : t w 50% t f 50% t r 50% ? waveform shift / load q v ol v oh 50% 50% 50% 50% 50% 90% 10% t thl 50% 90% t tlh t rem 50% t plh t su t phl t phl data 50% t f 50% t r t w 90% 10% 90% 90% 10% 10% 90% t n+1 t n t n+1 t n 50% 50% t h t su t h t su t rem 50% 90% 10% t thl 50% 50% t su t rem v cc 0 v v cc 0 v v cc 0 v
HD74HC195 rev.2.00 jan 31, 2006 page 7 of 7 package dimensions 7.62 dp-16fv renesas code jeita package code previous code max nom min dimension in millimeters symbol reference 19.2 6.3 5.06 mass[typ.] 1.05g a z b d e a b c e l 1 1 p 3 e 0.51 0.56 1.30 0.19 0.25 0.31 2.29 2.54 2.79 0 15 prdp0016ae-b p-dip16-6.3x19.2-2.54 20.32 7.4 0.40 0.48 1.12 2.54 1 p 1 3 1 8 16 9 e b a l a z e c e d b 0.89 ( ni/pd/au plating )
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